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Dual 8-,10-,12-Bit, High Bandwidth Multiplying DACs with Parallel Interface AD5428/AD5440/AD5447
FEATURES
10 MHz multiplying bandwidth Fast parallel interface (58 MSPS write cycle) AD7528 upgrade (AD5428) AD7547 upgrade (AD5447) 2.5 V to 5.5 V supply operation 10 V reference input 20- and 24-lead TSSOP packages Dual 8-, 10-, and 12-bit current output DACs Guaranteed monotonic 4-quadrant multiplication Power-on reset Readback function 0.5 A typical current consumption
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5428/AD5440/AD5447
VDD DATA INPUTS DB0 DB7 DB9 DB11 R RFBA IOUTA
INPUT BUFFER
LATCH
8-/10-/12-BIT R-2R DAC A
AGND DAC A/B R CS R/W LATCH DGND CONTROL LOGIC 8-/10-/12-BIT R-2R DAC B RFBB IOUTB
POWER-ON RESET
04462-0-001
VREFB
Figure 1. AD5428/AD5440/AD5447
APPLICATIONS
Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5428/AD5440/AD54471 are dual CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suited to battery-powered and other applications. The DACs utilize data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with zeros and the DAC outputs are at zero scale. As a result of manufacture on a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. The AD5428 is available in a small 20-lead TSSOP package, while the AD5440/AD5447 DACs are available in small 24-lead TSSOP packages.
1
US Patent Number 5,689,257.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5428/AD5440/AD5447 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 11 General Description................................................................... 16 Circuit Operation ....................................................................... 16 Single-Supply Applications........................................................ 18 Positive Output Voltage ............................................................. 19 Adding Gain................................................................................ 19 Used as a Divider or Programmable Gain Element............... 19 Reference Selection .................................................................... 20 Amplifier Selection .................................................................... 20 Parallel Interface......................................................................... 20 Microprocessor Interfacing....................................................... 20 PCB Layout and Power Supply Decoupling ........................... 21 Evaluation Board for the DACs................................................ 21 Power Supplies for the Evaluation board ................................ 21 Bill of Materials............................................................................... 25 Overview of AD54xx Devices....................................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 28
REVISION HISTORY
7/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5428/AD5440/AD5447 SPECIFICATIONS
Temperature range for Y version is -40C to +125C. VDD = 2.5 V to 5.5 V, VREFA = VREFB = +10 V, AGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP1177, AC performance with AD8038, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE AD5428 Resolution Relative Accuracy Differential Nonlinearity AD5440 Resolution Relative Accuracy Differential Nonlinearity AD5447 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp CoefficientT1 Output Leakage Current REFERENCE INPUT1 Reference Input Range VREFA, VREFB Input Resistance VREFA to VREFB Input Resistance Mismatch RFB A,RFBB Input Resistance Input Capacitance Code 0 Code 4095 DIGITAL INPUTS/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE1 Reference Multiplying BW Output Voltage Settling Time AD5428 AD5440 AD5447 Min Typ Max Unit Conditions
8 0.25 1 10 0.5 1 12 1 -1/+2 10 5 10 25 10 10 1.6 10 3 5 1.7 0.8 0.7 2 10 0.4 VDD -1 0.4 VDD - 0.5 10
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV ppm FSR/C nA nA V k % k pF pF V V V A pF V V V V MHz
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Data = 0000H, TA = 25C. Data = 0000H.
8
12 2.5 12 6 8
Input resistance TC = -50 ppm/C Typ = 25C, max = 125C Input resistance TC = -50 ppm/C
8
VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
4
ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A VREF = 3.5 V, DAC loaded all 1s VREF = 10 V, RLOAD = 100 , CLOAD = 15 pF DAC latch alternatively loaded with 0s and 1s Measured to 16 mV of FS Measured to 4 mV of FS Measured to 1 mV of FS
30 35 80
60 70 120
ns ns ns
Rev. 0 | Page 3 of 28
AD5428/AD5440/AD5447
Parameter Digital Delay 10% to 90% Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance IOUT2 IOUT1 Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR Performance (Wideband) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50k Hz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Intermodulation Distortion Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity1 Min Typ 20 15 2 Max 40 30 -75 22 10 12 25 1 -81 25 25 12 17 30 Unit ns Ns nV-s dB pF pF pF pF nV-s dB nV/Hz Conditions Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 1 LSB change around major carry, VREF = 0 V DAC latches loaded with all 0s. Reference = 10 kHz DAC latches loaded with all 0s DAC latches loaded with all 1s DAC latches loaded with all 0s DAC latches loaded with all 1s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz @ 1 kHz AD5447, 65 k codes, VREF = 3.5 V 55 63 65 50 60 62 dB dB dB dB dB dB AD5447, 65 k codes, VREF = 3.5 V 73 80 87 70 75 80 dB dB dB dB dB dB AD5447, 65 k codes, VREF = 3.5 V 65 72 51 65 2.5 0.5 5.5 0.6 10 0.001 dB dB dB dB V A A %/%
TA = 25C. Logic inputs = 0 V or VDD Logic inputs = 0 V or VDD VDD = 5%
1
Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 28
AD5428/AD5440/AD5447 TIMING CHARACTERISTICS
Temperature range for Y version is -40C to +125C. Guaranteed by design and characterization, not subject to production test. All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured with load circuit in Figure 3. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter Write Mode t1 t2 t3 t4 t5 t6 t7 t8 t9 Data Readback Mode t10 t11 t12 t13 Limit at TMIN, TMAX 0 0 10 10 0 6 0 5 7 0 0 5 25 5 10 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns typ ns typ ns max ns typ ns max Conditions/Comments R/W to CS setup time R/W to CS hold time CS low time Address setup time Address hold time Data setup time Data hold time R/W high to CS low CS min high time Address setup time Address hold time Data access time Bus relinquish time
R/W
t1
t2
t8
t2
t9
CS
t3 t4 t5 t10 t11
DACA/DACB
t8
DATA DATA VALID
DATA VALID
Figure 2. Timing Diagram
200A
IOL
TO OUTPUT PIN
VOH (MIN) + VOL (MAX) CL 50pF 200A IOH 2
04462-0-003
Figure 3. Load Circuit for Data Output Timing Specifications
Rev. 0 | Page 5 of 28
04462-0-002
t7
t12
t13
AD5428/AD5440/AD5447 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VREFA, VREFB, RFBA, RFBB to DGND IOUT1, IOUT2 to DGND Logic Inputs and Output1 Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature 20-lead TSSOP JA Thermal Impedance 24-lead TSSOP JA Thermal Impedance Lead Temperature, Soldering (10 seconds) IR Reflow, Peak Temperature (< 20 seconds)
1
Rating -0.3 V to +7 V -12 V to +12 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +150C 150C 143C/W 128C/W 300C 235C
Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Overvoltages at DBx, CS, and W/R are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 28
AD5428/AD5440/AD5447 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AGND 1 IOUTA 2 RFBA 3 VREFA 4 DGND 5 DAC A/B 6 DB7 7 DB6 8 DB5 9 DB4 10
20 19 18
IOUTB RFBB VREFB VDD R/W CS DB0 (LSB) DB1
04462-0-004
AD5428
TOP VIEW (Not to Scale)
17 16 15 14 13 12 11
DB2 DB3
Figure 4. Pin Configuration 20-Lead TSSOP (RU-20)
Table 4. AD5428 Pin Function Descriptions
Pin No. 1 2, 20 3, 19 4, 18 5 6 7 to14 15 16 17 Mnemonic AGND IOUTA, IOUTB RFBA, RFBB VREFA, VREFB DGND DAC A/B DB7 to DB0 CS R/W VDD Function DAC Ground Pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to achieve single-supply operation. DAC Current Outputs. DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output. DAC Reference Voltage Input Terminals. Digital Ground Pin. Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B. Parallel Data Bits 7 through 0. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back contents of the DAC register. Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. 0 | Page 7 of 28
AD5428/AD5440/AD5447
AGND 1 IOUTA 2 RFBA 3 VREFA 4 DGND 5 DAC A/B 6 DB9 7 DB8 8 DB7 9 DB6 10 DB5 11 DB4 12
24 23 22
IOUTB RFBB VREFB VDD R/W CS NC NC DB0 (LSB) DB1 DB2 DB3
04462-0-005
AD5440
TOP VIEW (Not to Scale)
21 20 19 18 17 16 15 14 13
NC = NO CONNECT
Figure 5. Pin Configuration 24-Lead TSSOP (RU-24)
Table 5. AD5440 Pin Function Descriptions
Pin No. 1 2, 24 3, 23 4, 22 5 6 7 to16 19 20 21 Mnemonic AGND IOUTA, IOUTB RFBA, RFBB VREFA, VREFB DGND DAC A/B DB9 to DB0 CS R/W VDD Function DAC Ground pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to achieve single-supply operation. DAC Current Outputs. DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output. DAC Reference Voltage Input Terminals. Digital Ground pPin. Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B. Parallel Data Bits 9 through 0. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back contents of the DAC register. Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. 0 | Page 8 of 28
AD5428/AD5440/AD5447
AGND 1 IOUTA 2 RFBA 3 VREFA 4 DGND 5 DAC A/B 6 DB11 7 DB10 8 DB9 9 DB8 10 DB7 11 DB6 12
24 23 22
IOUTB RFBB VREFB VDD R/W CS DB0 (LSB) DB1 DB2 DB3 DB4 DB5
04462-0-006
AD5447
TOP VIEW (Not to Scale)
21 20 19 18 17 16 15 14 13
Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)
Table 6. AD5447 Pin Function Descriptions
Pin No. 1 2, 24 3, 23 4, 22 5 6 7 to 18 19 Mnemonic AGND IOUTA, IOUTB RFBA, RFBB VREFA, VREFB DGND DAC A/B DB11 to DB0 CS Function DAC Ground pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to achieve single-supply operation. DAC Current Outputs. DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output. DAC Reference Voltage Input Terminals. Digital Ground Pin. Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B. Parallel Data Bits 11 through 0. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. When CS and R/W are held low, the latches are transparent; any changes on the data lines will be reflected on the relevant DAC output. Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back contents of DAC register. When CS and R/W are held low, the latches are transparent; any changes on the data lines are reflected on the relevant DAC output. Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
20
R/W
21
VDD
Rev. 0 | Page 9 of 28
AD5428/AD5440/AD5447 TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is typically expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of -1 LSB max over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to zero with external resistance. Output Leakage Current Output leakage current flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 resistor to ground. Digital-to-Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower-order harmonics are included, such as second to fifth.
THD = 20 log
(V22 +V32 + V42 + V52 )
V1
Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa - ffb and 2fb - fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonically- or nonharmonically-related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fs/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case 50%, of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is digitally generated sine wave.
Rev. 0 | Page 10 of 28
AD5428/AD5440/AD5447 TYPICAL PERFORMANCE CHARACTERISTICS
0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15
04462-0-007
0.20
TA = 25C VREF = 10V VDD = 5V
0.15 0.10 0.05 0 -0.05 -0.10 -0.15
TA = 25C VREF = 10V VDD = 5V
INL (LSB)
0
50
100 CODE
150
200
250
0
50
100 CODE
150
200
250
Figure 7. INL vs. Code (8-Bit DAC)
0.5 0.4 0.3 0.2 TA = 25C VREF = 10V VDD = 5V
0.5 0.4 0.3 0.2
Figure 10. DNL vs. Code (8-Bit DAC)
TA = 25C VREF = 10V VDD = 5V
DNL (LSB)
INL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4
04462-0-008
0.1 0 -0.1 -0.2 -0.3 -0.4
04462-0-011 04462-0-012
-0.5 0 200 400 CODE 600 800 1000
-0.5 0 200 400 CODE 600 800 1000
Figure 8. INL vs. Code (10-Bit DAC)
1.0 0.8 0.6 0.4 TA = 25C VREF = 10V VDD = 5V 1.0 0.8 0.6 0.4
Figure 11. DNL vs. Code (10-Bit DAC)
TA = 25C VREF = 10V VDD = 5V
0 -0.2 -0.4 -0.6 -0.8 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
04462-0-009
DNL (LSB)
INL (LSB)
0.2
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
-1.0
Figure 9. INL vs. Code (12-Bit DAC)
Figure 12. DNL vs. Code (12-Bit DAC)
Rev. 0 | Page 11 of 28
04462-0-010
-0.20
DNL (LSB)
-0.20
AD5428/AD5440/AD5447
0.6 0.5 0.4 MAX INL
8 TA = 25C 7 6
CURRENT (mA)
0.3
5 4 3 2 1 0 0 0.5 1.0 1.5
VDD = 5V
INL (LSB)
0.2 0.1 0 MIN INL -0.1 -0.2
04462-0-013
TA = 25C VREF = 10V VDD = 5V
VDD = 3V VDD = 2.5V
-0.3 2 3 4 5 6 7 8 9 10 REFERENCE VOLTAGE
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
Figure 13. INL vs. Reference Voltage
-0.40 TA = 25C VREF = 10V VDD = 5V
Figure 16. Supply Current vs. Logic Input Voltage
1.6 1.4 1.2
-0.45
-0.50
IOUT1 VDD 5V
IOUT LEAKAGE (nA)
1.0 0.8 IOUT1 VDD 3V 0.6 0.4 0.2
04462-0-023 04462-0-024
DNL (LSB)
-0.55
-0.60 MIN DNL -0.65
04462-0-014
-0.70 2 3 4 5 6 7 8 9 10 REFERENCE VOLTAGE
0 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 14. DNL vs. Reference Voltage
5 4 3 2 VDD = 5V 0.50 0.45
Figure 17. IOUT1 Leakage Current vs. Temperature
TA = 25C VDD = 5V
0.40 0.35
CURRENT (A)
ALL 0s 0.30 0.25 0.20 0.15 0.10 ALL 1s ALL 0s VDD = 2.5V ALL 1s
ERROR (mV)
1 0 -1 -2 -3 -4 -5 -60 VREF = 10V
04462-0-015
VDD = 2.5V
0.05 0 -60
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (C)
TEMPERATURE (C)
Figure 15. Gain Error vs. Temperature
Figure 18. Supply Current vs. Temperature
Rev. 0 | Page 12 of 28
04462-0-022
AD5428/AD5440/AD5447
14 TA = 25C LOADING ZS TO FS VDD = 5V
3 TA = 25C VDD = 5V
12
10
0
IDD (mA)
8 6
GAIN (dB)
-3
VDD = 3V
4 VDD = 2.5V 2
-6
VREF = 2V, AD8038 CC 1.47pF VREF = 2V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1.47pF VREF = 3.51V, AD8038 CC 1.8pF 100k 1M FREQUENCY (Hz) 10M 100M
04462-0-028
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
04462-0-025
0
-9 10k
Figure 19. Supply Current vs. Update Rate
6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 1
Figure 22. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor
0.045 0.040 0.035 VDD = 5V
TA = 25C LOADING ZS TO FS
OUTPUT VOLTAGE (V)
ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
7FF TO 800H
TA = 25C VREF = 0V AD8038 AMPLIFIER CCOMP = 1.8pF
0.030 0.025 0.020 0.015 800 TO 7FFH 0.010 0.005 0 VDD = 3V VDD = 3V
GAIN (dB)
ALL OFF 10
100 1k 10k 100k FREQUENCY (Hz)
04462-0-026
TA = 25C VDD = 5V VREF = 3.5V INPUT CCOMP = 1.8pF AD8038 AMPLIFIER
1M 10M 100M
-0.005 0 20 40 60 80 100 120 140 160 180 200
04462-0-041
-0.010
VDD = 5V
TIME (ns)
Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 23. Midscale Transition, VREF = 0 V
0.2
-1.68 7FF TO 800H -1.69 TA = 25C VREF = 3.5V AD8038 AMPLIFIER CCOMP = 1.8pF
0
VDD = 5V -1.70
OUTPUT VOLTAGE (V)
GAIN (dB)
-0.2
-1.71 -1.72 -1.73 -1.74 -1.75 -1.76 800 TO 7FFH VDD = 3V VDD = 5V VDD = 3V
-0.4
-0.6
TA = 25C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AD8038 AMPLIFIER
04462-0-027
-0.8 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
0
20
40
60
80
100
120
140
160
180
200
TIME (ns)
Figure 21. Reference Multiplying Bandwidth-All Ones Loaded
Figure 24. Midscale Transition, VREF = 3.5 V
Rev. 0 | Page 13 of 28
04462-0-042
-1.77
AD5428/AD5440/AD5447
20 0 -20 TA = 25C VDD = 3V AMP = AD8038
90 80 MCLK = 5MHz 70 60 MCLK = 10MHz
PSRR (dB)
-40
SFDR (dB)
FULL SCALE
-60 -80
50 40 30 20 MCLK = 25MHz
ZERO SCALE
-100
10
-120
04462-0-043
TA = 25C VREF = 3.5V AD8038 AMPLIFIER 0 100 200 300 400 500 600 700 800 900 1000
04462-0-046
1
10
100
1k
10k
100k
1M
10M
0
FREQUENCY (Hz)
fOUT (kHz)
Figure 25. Power Supply Rejection vs. Frequency
-60 TA = 25C VDD = 3V VREF = 3.5V p-p
Figure 28. Wideband SFDR vs. fOUT Frequency
0
-65
-10
-20
TA = 25C VDD = 5V AMP = AD8038 65k CODES
-70
-30
SFDR (dB)
-40
THD + N (dB)
-75
-50
-60
-80
-70
-85
-80
04462-0-044
-90 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)
-90
0 2 4 6 8 FREQUENCY (MHz) 10 12
Figure 26. THD + Noise vs. Frequency
100 MCLK = 1MHz 80 0 -10 -20 -30
Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
TA 25C = VDD = 5V AMP = AD8038 65k CODES
SFDR (dB)
60
MCLK = 200kHz MCLK = 0.5MHz
SFDR (dB)
-40 -50 -60 -70
40
20 TA = 25C VREF = 3.5V AD8038 AMPLIFIER
04462-0-045
-80 -90 -100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) 4.0 4.5 5.0
044620-048
0 0 20 40 60 80 100 120 140 160 180 200
fOUT (kHz)
Figure 27. Wideband SFDR vs. fOUT Frequency
Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Rev. 0 | Page 14 of 28
04462-0-047
AD5428/AD5440/AD5447
0 -10 -20 -30
SFDR (dB)
TA = 25C VDD = 5V AMP = AD8038 65k CODES
0 -10 -20 -30 -40
(dB)
TA 25C = VDD = 3V AMP = AD8038 65k CODES
-40 -50 -60 -70 -80
04462-0-049
-50 -60 -70 -80 -90
-90
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) 4.0 4.5 5.0
-100 70 75 80 85 95 90 100 105 FREQUENCY (MHz) 110 115 120
Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
0 -10 -20 -30 -40
SFDR (dB)
Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
0 -10 -20 -30 -40
(dB)
TA 25C = VDD = 3V AMP = AD8038 65k CODES
TA 25C = VDD = 5V AMP = AD8038 65k CODES
-50 -60 -70 -80 -90
04462-0-050
-50 -60 -70 -80 -90
-100 250
-100 0 50 100 150 200 250 FREQUENCY (kHz) 300 350 400
300
350
400
450 500 550 600 FREQUENCY (MHz)
650
700
750
Figure 32. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
20 0 -20
Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
300 ZERO SCALE LOADED TO DAC 250 MIDSCALE LOADED TO DAC FULL SCALE LOADED TO DAC
TA 25C = VDD = 3V AMP = AD8038 65k CODES
OUTPUT NOISE (nV/ Hz)
TA = 25C AMP = AD8038
200
SFDR (dB)
-40 -60 -80
150
100
-100
04462-0-051
50
04462-0-054
-120 50
60
70
80
90 100 110 120 FREQUENCY (MHz)
130
140
150
0 100
1k
10k FREQUENCY (Hz)
100k
Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 36. Output Noise Spectral Density
Rev. 0 | Page 15 of 28
04462-0-053
04462-0-052
AD5428/AD5440/AD5447
GENERAL DESCRIPTION
The AD5428, AD5440 and AD5447 are dual 8-, 10- and 12-bit current output DACs consisting of a standard inverting R-2R ladder configuration. A simplified diagram for the 8-bit AD5428 is shown in Figure 37. The feedback resistor RFB has a value of R. The value of R is typically 10 k (minimum 8 k and maximum 12 k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of value R. The DAC output (IOUT) is code dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the DAC on the amplifier's inverting input node.
VREF R 2R S1 R 2R S2 2R S3 R 2R S8 2R R RFBA
04462-0-029
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 38. When an output amplifier is connected in unipolar mode, the output voltage is given by
VOUT = - VREF x D / 2n
where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. D = 0 to 255 (8-bit AD5428) = 0 to 1023 (10-bit AD5440) = 0 to 4095 (12-bit AD5447) Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal digital logic to drive the on and off states of the DAC switches. These DACs are also designed to accommodate ac reference input signals in the range of -10 V to +10 V. With a fixed 10 V reference, the circuit in Figure 8 gives a unipolar 0 V to -10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. The following table shows the relationship between digital code and the expected output voltage for unipolar operation (AD5428, 8-bit device). Table 7. Unipolar Code Table
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) -VREF (255/256) -VREF(128/256) = -VREF/2 -VREF (1/256) -VREF (0/256) = 0
IOUT1 IOUT2 DAC DATA LATCHES AND DRIVERS
Figure 37. Simplified Ladder
Access is provided to the VREF, RFB, and IOUT terminals of DAC A and DAC B, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, 4-quadrant multiplication in bipolar mode or in single-supply modes of operation. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity.
Rev. 0 | Page 16 of 28
AD5428/AD5440/AD5447
VINA (10V) R11
AD5428/AD5440/AD5447
VDD
VREFA R RFBA R21 C12
DATA INPUTS
DB0 INPUT BUFFER DB7 DB9 DB11 LATCH 8-/10-/12-BIT R-2R DAC A
IOUTA VOUTA
AGND
AGND
DAC A/B CS R/W LATCH DGND CONTROL LOGIC 8-/10-/12-BIT R-2R DAC B
R
RFBB
R41 C22
IOUTB VOUTB
AGND POWER-ON RESET VREFB
R31 VINB (10V) NOTES: 1 R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2 C1, C2 PHASE COMPENSATION (1pF-2pF) IS REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
04462-0-030
Figure 38. Unipolar Operation
Bipolar Operation
In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors, as shown in Figure 39. In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF). When connected in bipolar mode, the output voltage is given by
Table 8. Bipolar Code Table
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) +VREF (127/128) 0 -VREF (127/128) -VREF (128/128)
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible and proper PCB layout techniques must be employed. Because every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open loop response which can cause ringing or instability in the closed loop applications circuit. An optional compensation capacitor, C1, can be added in parallel with RFB for stability, as shown in Figure 38 and in Figure 39. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to2 pF is generally adequate for the compensation.
VOUT = VREF x D / 2n-1 - VREF
where D is the fractional representation of the digital word loaded to the DAC, and n is the number of bits. D = 0 to 255 (AD5428) = 0 to 1023 (AD5440) = 0 to 4095 (AD5447) When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 8 shows the relationship between digital code and the expected output voltage for bipolar operation (AD5428, 8-bit device).
(
)
Rev. 0 | Page 17 of 28
AD5428/AD5440/AD5447
VINA (10V)
R11 VREFA R62 20k R72 10k C12 DATA INPUTS DB0 DB7 DB9 DB11 IOUTA INPUT BUFFER LATCH 8-/10-/12-BIT R-2R DAC A A1 AGND AGND
R5 20k
AD5428/AD5440/AD5447
VDD
A2 VOUTA R11 5k
R
RFBA
R21
AGND
DAC A/B CS R/W LATCH DGND 8-/10-/12-BIT R-2R DAC B CONTROL LOGIC
R
RFBB
R41 C22
IOUTB A3 R92 10k R8 20k
AGND POWER-ON RESET VREFB
R102 20k
A4 VOUTB R12 5k
R31
AGND
VINB (10V) NOTES: 1 R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V OUTA = 0V WITH CODE 10000000 IN DAC A LATCH. ADJUST R3 FOR VOUTB = 0V WITH CODE 10000000 IN DAC B LATCH. 2 MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10. 3 C1, C2 PHASE COMPENSATION (1pF-2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.
Figure 39. Bipolar Operation (4-Quadrant Multiplication)
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 40 shows these DACs operating in voltage-switching mode. The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage, making singlesupply operation possible. The output from the DAC is voltage at constant impedance (the DAC ladder resistance), thus an op amp is necessary to buffer the output voltage. The reference input no longer sees constant input impedance, but one that varies with code. So, the voltage input should be driven from a low impedance source. Note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same source-drain drive voltage. As a result, their on resistance differs and this degrades the integral linearity of the DAC. Also, VIN must not go negative by more than 0.3 V or an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost.
Rev. 0 | Page 18 of 28
VDD R1 R2
RFB VIN IOUT1 IOUT2
VDD VREF GND VOUT
1 ADDITIONAL PINS OMITTED FOR CLARITY. 2 C1 PHASE COMPENSATION (1pF-2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 40. Single-Supply Voltage-Switching Mode
04462-0-033
NOTES:
04462-0-031
AD5428/AD5440/AD5447
POSITIVE OUTPUT VOLTAGE
Note the output voltage polarity is opposite to the VREF polarity for dc reference voltages. For a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor's tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and -2.5 V respectively, as shown in Figure 41.
VDD = +5V
USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input resistor as shown in Figure 43, then the output voltage is inversely proportional to the digital input fraction D. For D = 1-2n the output voltage is
ADR03
VOUT VIN GND +5V -2.5V VDD VREF RFB C1
VOUT = -VIN / D = -VIN /(1 - 2n )
VDD VIN
1/2 AD8552
-5V
8-/10-/12-BIT IOUT1 DAC 2 I
OUT
VOUT = 0V to 2.5V
RFB IOUT1 IOUT2
VDD VREF GND
GND
1/2 AD8552
04462-0-034
1 2
NOTES: ADDITIONAL PINS OMITTED FOR CLARITY. C1 PHASE COMPENSATION (1pF-2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Positive Voltage Output with Minimum Components
VOUT
04462-0-040
ADDING GAIN
In applications where the output voltage is required to be greater than VIN, gain can be added with another external amplifier or it can also be achieved in a single stage. It is important to take into consideration the effect of temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit of Figure 42 shows the recommended method of increasing the gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of >1 are required.
VDD
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 43. Current-Steering DAC Used as a Divider or Programmable Gain Element
As D is reduced, the output voltage increases. For small values of the digital fraction D, it is important to ensure that the amplifier does not saturate and also that the required accuracy is met. For example, an 8-bit DAC driven with the binary code 0 x 10 (00010000)--that is, 16 decimal--in the circuit of Figure 43 should cause the output voltage to be 16 xVIN. However, if the DAC has a linearity specification of 0.5 LSB, then D can, in fact, have the weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage is in the range 15.5 VIN to 16.5 VIN--an error of 3% even though the DAC itself has a maximum error of 0.2%. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Because only a fraction, D, of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage must change to:
VDD VIN R2 VREF
RFB IOUT1 IOUT2
C1
8-/10-/12-BIT DAC
GND
VOUT R3 R2 GAIN = R1 = R2 + R3 R2
04462-0-035
1 2
NOTES: ADDITIONAL PINS OMITTED FOR CLARITY. C1 PHASE COMPENSATION (1pF-2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
R2R3 R2 + R3
Output Error Voltage Due to DAC Leakage = (Leakage x R )/ D
Figure 42. Increasing Gain of Current Output DAC
where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 k and a gain (i.e, a/D) of 16, the error voltage is 1.6 mV.
Rev. 0 | Page 19 of 28
AD5428/AD5440/AD5447
REFERENCE SELECTION
When selecting a reference for use with the AD54XX series of current output DACs, pay attention to the reference's output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0 to 50C dictates that the maximum system drift with temperature should be less than 78 ppm/C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/C. By choosing a precision reference with low output temperature coefficient this error source can be minimized. Table 9 lists some of the references available from Analog Devices, Inc. that are suitable for use with this range of current output DACs.
PARALLEL INTERFACE
Data is loaded to the AD5428/ AD5440/ AD5447 in the format of an 8-, 10-, or 12-bit parallel word. Control lines CS and R/W allow data to be written to or read from the DAC register. A write event takes place when CS and R/W are brought low, data available on the data lines fills the shift register, and the rising edge of CS latches the data and transfers the latched data word to the DAC register. The DAC latches are not transparent, thus a write sequence must consist of a falling and rising edge on CS to ensure data is loaded to the DAC register and its analog equivalent reflected on the DAC output. A read event takes place when R/W is held high and CS is brought low. Data is loaded from the DAC register back to the input register and out onto the data line where it can be read back to the controller for verification or diagnostic purposes. The input and DAC registers of these devices are not transparent, so a falling and rising edge of CS is required to load each data-word.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code-dependent output resistance of the DAC) of the circuit. A change in the noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed on the change in output between the two codes and gives rise to a differential linearity error, which if too large might cause the DAC to be nonmonotonic. The input offset voltage should be <1/4 LSB to ensure monotonic behavior when stepping through codes. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent significant errors in 12-bit applications. In voltage-switching circuits, common-mode rejection of the op amp is important because it produces a code-dependent error at the voltage output of the circuit. Most op amps have adequate common-mode rejection for use at 8-, 10-, and 12-bit resolution. Provided the DAC switches are driven from true wideband, low impedance sources (VIN and AGND), they settle quickly. Thus, the slew rate and settling time of a voltage-switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node (voltage output node in this application) of the DAC. This is done by using low input capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals. Analog Devices, Inc. provides a large variety of single-supply amplifiers.
MICROPROCESSOR INTERFACING
The AD5428/AD5440/AD5447 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 44 shows the AD54xx DAC interfaced to a generic 16-bit microcontroller/ DSP processor. Microprocessor interfacing to this family of DACs is via a data bus that uses standard protocol compatible with microcontrollers and DSP processors. The address decoder is used to select DAC A or DAC B and also to load parallel data to the input latch or to read data from the DAC using an AND gate.
A0 TO AX ADDRESS BUS
AD54XX*
MICRO/DSP*
ADDRESS DECODER A DAC A/B CS
A+1 WR
WR DB0 TO DB11
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. AD54xx to Parallel Interface
Rev. 0 | Page 20 of 28
04462-0-055
DB0 TO DB11
DATA BUS
AD5428/AD5440/AD5447
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5428/AD5440/AD5447 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGNDto-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the soldered side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize on high frequency performance, the I-to-V amplifier should be located as close to the device as possible.
EVALUATION BOARD FOR THE DACS
The evaluation board consists of a DAC and a current to voltage amplifier AD8065. Included on the evaluation board is a 10 V reference, ADR01. An external reference may also be applied via an SMB input. The evaluation kit consists of a CD-ROM with self-installing PC software to control the DAC. The software simply allows the user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires 12 V, and +5 V supplies. The +12 V VDD and Vss are used to power the output amplifier, while the +5 V is used to power the DAC (VDD1) and transceivers (VCC). Both supplies are decoupled to their respective ground plane with 10F tantalum and 0.1F ceramic capacitors.
Table 9. Suitable ADI Precision References Recommended for Use with AD5428/AD5440/AD5447 DACs
Reference ADR01 ADR02 ADR03 ADR425 Output Voltage 10 V 5V 2.5 V 5V Initial Tolerance 0.1% 0.1% 0.2% 0.04% Temperature Drift 3 ppm/C 3 ppm/C 3 ppm/C 3 ppm/C 0.1 Hz to 10 Hz noise 20 V p-p 10 V p-p 10 V p-p 3.4 V p-p Package SC70, TSOT, SOIC SC70, TSOT, SOIC SC70, TSOT, SOIC MSOP, SOIC
Table 10. Precision ADI Op Amps Suitable for Use with AD5428/AD5440/AD5447 DACs
Part # OP97 OP1177 AD8551 Max Supply Voltage V 20 18 +6 VOS (max) VIB(max) nA 25 60 5 IB (max) nA 0.1 2 0.05 GBP MHz 0.9 1.3 1.5 Slew Rate V/s 0.2 0.7 0.4
Table 11. High Speed ADI Op Amps Suitable for Use with AD5428/AD5440/AD5447 DACs
Part # AD8065 AD8021 AD8038 Max Supply Voltage V 12 12 5 BW @ ACL MHz 145 200 350 Slew Rate V/s 180 100 425 VOS (max) V 1500 1000 3000 IB (max) nA 0.01 1000 0.75
Rev. 0 | Page 21 of 28
VCC
VDD1 C5 10F +
C1 0.1F
U4 VCC 24 U1 AD5547
21 C23 10F C22 1.8pF 23 24 2 3 3 2 TP3 TP2 22 4 C26 0.1F C9 10F J2 J5 C7 1.8pF + VSS EXT REF B LK1 A B VOUT 4 2 3 4
V- V+
C6 0.1F
P1-7 P1-6 P1-5 P1-4 P1-3 P1-2
+ VSS 4
V- V+
AD5428/AD5440/AD5447
TP4 6 J6 O/P B
1 2 3 4 5 6 7 8 9 10 11 12 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND CEBA B7 B6 B5 B4 B3 B2 B1 B0 LEAB OEAB
C24 0.1F
23 15 16 17 18 19 20 21 22 14 13
VCC
74ABT543
U7
VDD
7
C25 10F +
C17 0.1F C2 0.1F
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11
DGND
U6-A
CS RW
5 DGND
VCC
P1-8
2
Y0
4
18 17 16 15 14 13 12 11 10 9 8 7 6 19 20
VDD DB0 DB1 DB2 DB3 DB4 RFBB DB5 IOUTB DB6 DB7 DB8 RFBA DB9 DB10 IOUTA DB11 DAC_A/B CS VREFA R/W VREFB DGND AGND 1
A0
P1-9
3
Y1
5
U5 VCC 24
A1
Y2
6
P1-36
EXT REF A
1
E
Y3
7
C10 0.1F 6
TP1 J1 O/P A
U3
VDD
7
1 2 3 4 5 6 7 8 9 10 11 12 23 15 16 17 18 19 20 21 22 J3
VDD
C11 10F +
3 +V IN
J4
C3 10F + C4 0.1F
LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND CEBA B7 B6 B5 B4 B3 B2 B1 B0 14 LEAB 13 OEAB
Figure 45. Schematic of AD5428/AD5440/AD5447 Evaluation Board
Rev. 0 | Page 22 of 28
U2 5 TRIM
GND
74ABT543
1 2
C8 0.1F
C12 0.1F
P1-31
P1-1
P1-14
U6-B
14 A0 Y1 Y2 Y3 P2-1 VSS P2-4 VDD1 + A1 E DGND Y0
12 11 10 9
C15 0.1F C16 10F
+ P2-2 AGND P2-3
VDD
13 15
C13 0.1F C14 10F
C17 0.1F
P2-6
+
C18 10F
VCC
C19 0.1F
P2-5
+
C20 10F
04464-0-023
P1-19 P1-20 P1-21 P1-22 P1-23 P1-24 P1-25 P1-26 P1-27 P1-28 P1-29 P1-30
AD5428/AD5440/AD5447
Figure 46. Component-Side Artwork
Figure 47. Silkscreen--Component-Side View (Top Layer)
Rev. 0 | Page 23 of 28
04462-0-038
04462-0-036
AD5428/AD5440/AD5447
Figure 48. Solder-Side Artwork
Rev. 0 | Page 24 of 28
04462-0-039
AD5428/AD5440/AD5447 BILL OF MATERIALS
Table 12.
Name C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 CS, DB0-11 J1-6 J2 J3 J4 J5 J6 LK1 P1 P2 RW TP1 to 4 U1 U2 U3 U4, U5 U6 U7 Each Corner Part Description X7R Ceramic Capacitor X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor NPO Ceramic Capacitor X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor NPO Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor Tantalum Capacitor--Taj Series X7R Ceramic Capacitor Red Testpoint SMB Socket SMB Socket SMB Socket SMB Socket SMB Socket SMB Socket 3-Pin Header (2x2) 36-Pin Centronics Connector 6-Pin Terminal Block Red Testpoint Red Testpoint AD5428/AD5440/AD5447 ADR01 AD8065 74ABT543 74139 AD8065 Rubber Stick-On Feet Value 0.1 uF 0.1 uF 10 uF 20 V 0.1 uF 10 uF 10 V 0.1 uF 1.8 pF 0.1 uF 10 uF 20 V 0.1 uF 10 uF 20 V 0.1 uF 0.1 uF 10 uF 20 V 0.1 uF 10 uF 20 V 0.1 uF 10 uF 20 V 0.1 uF 10 uF 20 V 0.1 uF 1.8 pF 10 uF 20 V 0.1 uF 10 uF 20 V 0.1 uF Tolerance (%) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Stock Code FEC 499-675 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-130 FEC 499-675 FEC 721-876 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 721-876 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 240-345 (Pack) FEC 310-682 FEC 310-682 FEC 310-682 FEC 310-682 FEC 310-682 FEC 310-682 FEC 511-791&528-456 FEC 147-753 FEC 151-792 FEC 240-345 (Pack) FEC 240-345 (Pack) AD5428YRU / AD5440YRU / AD5447YRU ADR01AR AD8065AR Fairchild 74ABT543CMTC CD74HCT139M AD8065AR FEC 148-922
Rev. 0 | Page 25 of 28
AD5428/AD5440/AD5447 OVERVIEW OF AD54xx DEVICES
Table 13.
Part No. AD5424 AD5426 AD5428 AD5429 AD5450 AD5432 AD5433 AD5439 AD5440 AD5451 AD5443 AD5444 AD5415 AD5445 AD5447 AD5449 AD5452 AD5446 AD5453 AD5553 AD5556 AD5555 AD5557 AD5543 AD5546 AD5545 AD5547 Resolution 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16 No. DACs 1 1 2 2 1 1 1 2 2 1 1 1 2 2 2 2 1 1 1 1 1 2 2 1 1 2 2 INL(LSB) 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.25 1 0.5 1 1 1 1 0.5 1 2 1 1 1 1 2 2 2 2 Interface Parallel Serial Parallel Serial Serial Serial Parallel Serial Parallel Serial Serial Serial Serial Parallel Parallel Serial Serial Serial Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel Package RU-16, CP-20 RM-10 RU-20 RU-10 RJ-8 RM-10 RU-20, CP-20 RU-16 RU-24 RJ-8 RM-10 RM-8 RU-24 RU-20, CP-20 RU-24 RU-16 RJ-8, RM-8 RM-8 UJ-8, RM-8 RM-8 RU-28 RM-8 RU-38 RM-8 RU-28 RU-16 RU-38 Features 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 58 MHz Serial 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 17 ns CS Pulse Width 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 10 MHz BW, 50 MHz Serial 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width 4 MHz BW, 50 MHz Serial Clock 4 MHz BW, 20 ns WR Pulse Width
Rev. 0 | Page 26 of 28
AD5428/AD5440/AD5447 OUTLINE DIMENSIONS
6.60 6.50 6.40
20
11
4.50 4.40 4.30 6.40 BSC
1 10
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AC
Figure 49. 20-Lead TSSOP (RU-20) Dimensions shown in millimeters
7.90 7.80 7.70
24
13
4.50 4.40 4.30 6.40 BSC
1 12
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD 1.20 MAX
SEATING PLANE
0.20 0.09
8 0
0.75 0.60 0.45
Figure 50. 24-Lead TSSOP (RU-24) Dimensions shown in millimeters
Rev. 0 | Page 27 of 28
AD5428/AD5440/AD5447
ORDERING GUIDE
Model AD5428YRU AD5428YRU-REEL AD5428YRU-REEL7 AD5440YRU AD5440YRU-REEL AD5440YRU-REEL7 AD5447YRU AD5447YRU-REEL AD5447YRU-REEL7 EVAL-AD5428EB EVAL-AD5440EB EVAL-AD5447EB Resolution 8 8 8 10 10 10 12 12 12 INL (LSBs) 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1 Temperature Range -40 C to +125C -40 C to +125C -40 C to +125C -40 C to +125C -40 C to +125C -40 C to +125C -40 C to +125C -40 C to +125C -40 C to +125C Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) Evaluation Kit Evaluation Kit Evaluation Kit Package Option RU-20 RU-20 RU-20 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04462-0-7/04(0)
Rev. 0 | Page 28 of 28
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